Delay Analysis in Carbon Nanotube Bundle Interconnect For VLSI Design
نویسنده
چکیده
This paper proposes to study the performance of carbon nanotube bundle in terms of delay as a VLSI interconnect at 32nm technology node. Output waveform and 90% propagation delay are analytically determined and compared with SPICE simulation result. Alpha power law model is used for representing the transistors of CMOS driver. SPICE simulation result reveals that delay increases with increase in length of interconnect.
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